A multi-processing system includes a plurality of processors that share a single memory. Typically, multi-level caches are used to reduce memory bandwidth demands on the single memory. The multi-level caches may include a first-level private cache in each processor and a second-level cache shared by all of the processors. As the cache is much smaller than the memory in the system, only a portion of the data stored in buffers/blocks in memory is replicated in the cache.
If data stored in a buffer/block requested by a processor is replicated in the cache, there is a cache hit. If the requested data is not replicated in the cache, there is a cache miss and the requested block that stores the data is retrieved from memory and also stored in the cache.
When shared data is cached, the shared value may be replicated in multiple first-level caches. Thus, caching of shared data requires cache coherence. Cache coherence ensures that multiple processors see a consistent view of memory, for example, a read of the shared data by any of the processors returns the most recently written value of the data.
Typically, blocks of memory (cache blocks) are replicated in cache and each cache block has an associated tag that includes a so-called dirty bit. The state of the dirty bit indicates whether the cache block has been modified. In a write back cache, the modified cache block is written back to memory only when the modified cache block is replaced by another cache block in the cache.